Understanding Logical Memory

  • 10091598
  • NOVL95859
  • 26-Feb-2004
  • 26-Feb-2004

Archived Content: This information is no longer maintained and is provided 'as is' for your convenience.

Fact

Novell eDirectory 8.7.3 for All Platforms

Novell eDirectory 8.7.1 for All Platforms

Novell NetWare 6.5

Novell NetWare 6

Novell NetWare 5.1

Goal

Understanding Logical Memory

Fix

Primer:

Logical (Virtual) memory vs. Physical memory

In order to provide the benefits of enhancing total system memory available to processes virtual memory is mapped into the existing physical memory of a system.  This is acheived by the creation of logical addresses which are generated by the CPU and are bound to a "real" Physical address. This is done by the MMU (Memory Management Utility) controller which maps the virtual  address to a physical one.  It does this via a relocation register.  The value in this register is added to every address generated by a user process at the time it is sent to memory.  The user program only knows about the logical address.  It never sees the "real" physical addresses.  This is central to proper memory management and allows for many cool functions:
- a process can be larger than the memory allocated to it
- routines are not loaded till called
- a process can be swapped temporarily out of memory to a backing store (read swap file) then be brought back into memory for continued execution.
- simplifies programming.

Executions can only run in real memory.  They cannot be run, for instance, from a logical address space swapped to disk.  We must be able to link the logical address to a real physical address in order to perform the code execution.  This is done by the relocation register.

Logical space is divided into units called pages.  The smallest page size is 4K.  In order to keep track of these page associations and be able to link back and forth between real addresses and virtual memory addresses a page table is created and kept in main memory.  This is refered to as Virtual Address Overhead which is affected by the size of the page table.  The more real memory a server holds the larger the page table must be. Since the table must be held in memory we in turn actually have less memory availble to the OS as the additional memory added is mapped into memory via the page table which in turn itself grows larger.

Fragmentation:

When a process requests memory the OS looks at the logical address space and assigns a page of memory equal to the request.  This allocation of memory requires that it be contiguous memory.  When the memory is released by the process NetWare's garbage collection then frees up this memory for use by another process.  The default time for garbage collection in NetWare 6.5 is 4 min 59.9 secs.  Allocations can be either long term allocations or short term allocations.  Many processes such as eDirectory can make many such requests using a mixture of both long term and short term allocation requests.  If a short term allocation is released but a long term allocation exists in this area of memory we cannot free up the entire "chunk" until all the requests have been flushed.  Till this occurs garbage collection cannot make this memory available for re-allocation and thus the memory remains "fragmented" and though unused is still unavailble for the next processes request.


NetWare Memory Facts:

NetWare 6.5 requires a minimum of 512 MB of RAM and can access up to 64 GB of RAM. After the server.exe file is loaded, the remaining memory below 4 GB is assigned to cache memory and virtual memory, which is available for NetWare Loadable ModuleTM (NLMTM) programs and other processes to use.
The memory allocator can not allocate memory above 4 GB. Intel's PAE (Physical Address Extension) in Pentium Pro's and newer allow for a maximum addressable memory space of 64GB.  However NetWare itself can only take advantage of the first 4GB.  Other services such as NSS can use this. The traditional file system does not use memory above 4 GB. 
Summary:


 Summary

 The x86 architecture is limited by the design of its addressing modes
and page tables to accessing 4GB of virtual memory.  This is a hard
limit.
 PAE mode (Physical Address Extensions) allows the processor to address
64GB of physical memory via the page tables, but does not change the
size of the virtual address space.

 

Return to Master Memory Document [no longer available]

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